During module assembly the process of joining a silicon die (device) to the substrate (chip carrier) involves creating a metallurgical joint between solder connections, e.g., controlled collapse chip connections (C4s), and the chip carrier. Defects, though, can occur during this joining process, known as non-contact non-wet (no contact between metallurgical joint) and contact non-wet (some electrical contact), resulting in failure to make the required conductive metallurgical joint. The most common location of C4 non wets is the highest DNP, distance to neutral point, or farthest location from the center of the chip. These defects occur more often in lead free C4s, 50 micron C4s, and coreless laminates.
Currently, chip join effectiveness is monitored by post chip join side inspection. Although this can be effective in certain instances, this method is limited to only the first few rows from the edge of the chip carrier. By way of example, an approach to monitoring chip join effectiveness is chip pull or chip shear. This type of testing is a destructive test. Accordingly, even if it is found that the chip connections (e.g., C4s) have all joined well, it is still necessary to discard the module. Also, opens at module test can be evaluated for the presence of C4 non wets but at that point it is many operations away from the chip join process and knowing what specific parameters about the process that may have lead to the condition is more difficult.
In addition, due to CTE (coefficient of thermal expansion) mismatch a fundamental technology issue requires the use of certain techniques to address the chip join problem in an iterative fashion. These techniques can include compensated laminates, compensated silicon or both.
Specific process conditions can also influence the factors that affect the formation of non wets (which results in failure to make a conductive metallurgical join), e.g., controlled ramp rates or cool downs. Again the effectiveness of these process changes cannot be fully known until the module (e.g., die and chip carrier) has been completed through assembly and tested.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.